Method to limit the time a semiconductor device operates above a maximum operating voltage

US11817697B2 · kind B2 · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Adam B. Collura · Hopewell Junction, US
• Michael Romain · Beacon, US
• William V. Huott · Holmes, US
• Pawel Owczarczyk · Highland, US
• Christian Jacobi · West Park, US
• Anthony Saporito · Highland, US
• Chung-Lung K. Shum · Wappingers Falls, US
• Alper Buyuktosunoglu · White Plains, US
• Tobias Webel · Eppelheim, DE
• Michael J. Cadigan, Jr. · Poughkeepsie, US
• Paul Jacob Logsdon · Poughkeepsie, US
• Sean Michael Carey · Hyde Park, US
• Stefan Payer · Stuttgart, DE
• Karl Evan Smock Anderson · Poughkeepsie, US
• Mark Cichanowski · Hutto, US

Key dates

• Filing date: Apr 5, 2022
• Grant date: Nov 14, 2023
• Expiry date: Jul 1, 2042

Classification

• Technology area (CPC H): Electricity
• CPC primary: H02H11/006
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

The method and systems described herein provide for identifying and mitigating undesirable power or voltage fluctuations in regions of a semiconductor device. For example, embodiments include detecting a region, such as an individual processor, of a processor chip is exhibiting a reduced power draw and a resulting localized voltage spike (e.g., a spike that exceeds Vmax) that would accelerate overall device end-of-life (EOL). The described systems respond by activating circuits or current generators located in the given region to draw additional power via a protective current. The protective current lowers the local voltages spikes back to within some pre-specified range (e.g., below a Vmax). The resulting reduction in the time above Vmax in testing reduces the number of devices that will need to be discarded due to Vmax violations as well as increases the expected reliability and lifespan of the device in operation.