Inventor · Stuttgart, DE

Stefan Payer

27Patents
2h-index
41Co-inventors
53Inventor score

Filing activity: Jan 5, 2012 → Apr 5, 2022

Most-cited inventions

PatentTitleAreaCited byStatus
US10169451B1 Rapid character substring searching Electricity 9 Active
US8659963B2 Enhanced power savings for memory arrays Physics 3 Active
US8918749B2 Integrated circuit schematics having imbedded scaling information for generating a design instance Physics 2 Active
US10747819B2 Rapid partial substring matching Physics 1 Active
US9704567B1 Stressing and testing semiconductor memory cells Physics 1 Active
US9977680B2 Clock-gating for multicycle instructions Emerging Cross-Sectional Technologies 1 Active
US11817697B2 Method to limit the time a semiconductor device operates above a maximum operating voltage Electricity 0 Active
US11663270B2 Vector string search instruction Physics 0 Active
US11068541B2 Vector string search instruction Physics 0 Active
US10732972B2 Non-overlapping substring detection within a data element string Physics 0 Active
US9805823B1 Automated stressing and testing of semiconductor memory cells Physics 0 Active
US11221826B2 Parallel rounding for conversion from binary floating point to binary coded decimal Electricity 0 Active
US11042371B2 Plausability-driven fault detection in result logic and condition codes for fast exact substring match Physics 0 Active
US12056465B2 Verifying the correctness of a leading zero counter Physics 0 Active
US10996951B2 Plausibility-driven fault detection in string termination logic for fast exact substring match Physics 0 Active
US9837142B1 Automated stressing and testing of semiconductor memory cells Physics 0 Active
US12190078B2 Rounding hexadecimal floating point numbers using binary incrementors Physics 0 Active
US10782968B2 Rapid substring detection within a data element string Physics 0 Active
US11210064B2 Parallelized rounding for decimal floating point to binary coded decimal conversion Electricity 0 Active
US11175921B2 Cognitive binary coded decimal to binary number conversion hardware for evaluating a preferred instruction variant based on feedback Physics 0 Active
US10983159B2 Method and apparatus for wiring multiple technology evaluation circuits Physics 0 Active
US10890622B2 Integrated circuit control latch protection Physics 0 Active
US11256511B2 Instruction scheduling during execution in a processor Physics 0 Active
US10552167B2 Clock-gating for multicycle instructions Emerging Cross-Sectional Technologies 0 Active
US9715944B1 Automatic built-in self test for memory arrays Physics 0 Active

Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.