Patent · US Active

Memory device and fabrication method thereof

US11818891B2 · kind B2 · utility

0Cited by
3References
20Claims
0Family size

Assignee

Inventors

Key dates

Filing dateJun 9, 2022
Grant dateNov 14, 2023
Priority date
Expiry dateJun 9, 2042

Classification

  • Technology area (CPC H)Electricity
  • CPC primaryH10D62/115

Abstract

A memory device includes a staircase region and an array region, along a first lateral direction; a wall structure in the staircase region; and a first separation structure in the array region and arranged along the first lateral direction with the wall structure. The wall structure includes dielectric pairs of a first dielectric layer and a second dielectric layer stacked in the staircase region. The first separation structure is vertically through a stack structure in the array region. The stack structure includes pairs of the first dielectric layer and an electrode layer.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.