Resistive random access memory and manufacturing method thereof
US11818966B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 3, 2021 |
| Grant date | Nov 14, 2023 |
| Priority date | — |
| Expiry date | Apr 11, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10N70/861
Abstract
Provided are a resistive random access memory and a manufacturing method thereof. The resistive random access memory includes a substrate having a pillar protruding from a surface of the substrate, a gate surrounding a part of a side surface of the pillar, a gate dielectric layer, a first electrode, a second electrode, a variable resistance layer, a first doped region and a second doped region. The gate dielectric layer is disposed between the gate and the pillar. The first electrode is disposed on a top surface of the pillar. The second electrode is disposed on the first electrode. The variable resistance layer is disposed between the first electrode and the second electrode. The first doped region is disposed in the pillar below the gate and in a part of the substrate below the pillar. The second doped region is disposed in the pillar between the gate and the first electrode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.