Pipelined out of order page miss handler
US11822486B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jun 27, 2020 |
| Grant date | Nov 21, 2023 |
| Priority date | — |
| Expiry date | Mar 24, 2042 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Systems, methods, and apparatuses relating to circuitry to implement a pipelined out of order page miss handler are described. In one embodiment, a hardware processor core includes an execution circuit to generate data storage requests for virtual addresses, a translation lookaside buffer to translate the virtual addresses to physical addresses, and a single page miss handler circuit comprising a plurality of pipelined page walk stages, wherein the single page miss handler circuit is to contemporaneously perform a first page walk within a first stage of the plurality of pipelined page walk stages for a first miss of a first virtual address in the translation lookaside buffer, and a second page walk within a second stage of the plurality of pipelined page walk stages for a second miss of a second virtual address in the translation lookaside buffer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.