Apparatus and method for masking power consumption of a processor
US11822705B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 29, 2021 |
| Grant date | Nov 21, 2023 |
| Priority date | — |
| Expiry date | Dec 3, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L9/003
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus for masking power consumption associated with one or more operations of a logic circuitry of a processor. The apparatus comprises power-complementing circuitry configured to provide a second power consumption to directly power-complementing the power consumption associated with the one or more operations of the logic circuitry. The second power consumption complements the power consumption associated with the one or more operations of the logic circuitry. The apparatus further comprises header circuitry configured to enable a common node to vary in voltage corresponding to the one or more operations of the logic circuitry. The power-complementing circuitry and the header circuitry are each coupled to the logic circuitry at the common node.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.