Chip with bifunctional routing and associated method of manufacturing
US11823997B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 20, 2021 |
| Grant date | Nov 21, 2023 |
| Priority date | — |
| Expiry date | Mar 24, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10N69/00
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A functional chip includes a substrate including a first face and a second face, the second face of the substrate forming the front face of the functional chip; a first oxide layer on the first face of the substrate; a second oxide layer on the first oxide layer; a first routing level formed on the surface of the second oxide layer in contact with the first oxide layer; a third oxide layer on the second oxide layer wherein a semiconductor component is inserted; a rear face formed by the surface of the third oxide layer opposite the second oxide layer, the rear face including superconductor routing tracks surrounded at least partially by one or more conductor routing tracks, the semiconductor component being connected to the superconductor routing tracks via superconductor vias and the conductor routing tracks of the rear face being connected to the routing level via conductor vias.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.