Integration of p-channel and n-channel E-FET III-V devices with optimization of device performance
US11824109B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 20, 2022 |
| Grant date | Nov 21, 2023 |
| Priority date | — |
| Expiry date | Jul 20, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/85
Abstract
Various embodiments of the present disclosure are directed towards an integrated chip a first undoped layer overlies a substrate. A first barrier layer overlies the first undoped layer and has a first thickness. A first doped layer overlies the first barrier layer and is disposed laterally within an n-channel device region of the substrate. A second barrier layer overlies the first barrier layer and is disposed within a p-channel device region that is laterally adjacent to the n-channel device region. The second barrier layer has a second thickness that is greater than the first thickness. A second undoped layer overlies the second barrier layer. A second doped layer overlies the second undoped layer. The second undoped layer and the second doped layer are disposed within the p-channel device region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.