One-time programmable memory structure
US11825648B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 18, 2021 |
| Grant date | Nov 21, 2023 |
| Priority date | — |
| Expiry date | Nov 24, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D1/692
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A one-time programmable memory structure including a substrate, a transistor, a capacitor, and an interconnect structure is provided. The transistor is located on the substrate. The capacitor includes a first electrode, a second electrode, and an insulating layer. The first electrode is disposed above the substrate. The second electrode is disposed on the first electrode. The first electrode is located between the second electrode and the substrate. The insulating layer is disposed between the first electrode and the second electrode. The interconnect structure is electrically connected between the transistor and the first electrode of the capacitor. The interconnect structure is electrically connected to the first electrode at a top surface of the first electrode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.