Patent · US Active

Memory network processor

US11829320B2 · kind B2 · utility

0Cited by

7References

16Claims

0Family size

Assignee

Coherent Logix, Incorporated · US

Inventors

Carl S. Dobbs · Austin, US
Keith M. Bindloss · Irvine, US
Kenneth R. Faulkner · Austin, US
Alex E. Icaza · Austin, US
Frederick Rush · Austin, US
Faisal A. Syed · Austin, US
Michael R. Trocino · Austin, US

Key dates

Filing date	Oct 20, 2022
Grant date	Nov 28, 2023
Priority date	—
Expiry date	Oct 20, 2042

Classification

Technology area (CPC Y)Emerging Cross-Sectional Technologies
CPC primaryY02D10/00
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

A multi-processor system with processing elements, interspersed memory, and primary and secondary interconnection networks optimized for high performance and low power dissipation is disclosed. In the secondary network multiple message routing nodes are arranged in an interspersed fashion with multiple processors. A given message routing node may receive messages from other message nodes, and relay the received messages to destination message routing nodes using relative offsets included in the messages. The relative offset may specify a number of message nodes from the message node that originated a message to a destination message node.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.