Self-aligned scheme for semiconductor device and method of forming the same
US11830770B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 20, 2022 |
| Grant date | Nov 28, 2023 |
| Priority date | — |
| Expiry date | May 20, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L23/53266
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Semiconductor device and the manufacturing method thereof are disclosed herein. An exemplary semiconductor device comprises an interlayer dielectric (ILD) layer disposed over a substrate; a first conductive feature at least partially embedded in the ILD layer; a dielectric layer disposed over and aligned with the ILD layer, wherein a top surface of the dielectric layer is above a top surface of the first conductive feature; an etch stop layer (ESL) disposed over the dielectric layer and over the first conductive feature; and a second conductive feature disposed on the first conductive feature, wherein the second conductive feature includes a first portion having a first bottom surface contacting a top surface of the first conductive feature and a second portion having a second bottom surface contacting a top surface of the dielectric layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.