Packaged transistor having die attach materials with channels and process of implementing the same
US11830810B2 · kind B2 · utility
1Cited by
10References
22Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 30, 2020 |
| Grant date | Nov 28, 2023 |
| Priority date | — |
| Expiry date | Oct 30, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/1423
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A package includes a circuit that includes at least one active area and at least one secondary device area, a support configured to support the circuit, and a die attach material. The circuit being mounted on the support using the die attach material and the die attach material including at least one channel configured to allow gases generated during curing of the die attach material to be released from the die attach material.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.