Reduced resistivity for access lines in a memory array
US11830816B2 · kind B2 · utility
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10Claims
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Key dates
| Filing date | Aug 14, 2020 |
| Grant date | Nov 28, 2023 |
| Priority date | — |
| Expiry date | Jan 10, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L23/5386
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Methods, systems, and devices for reduced resistivity for access lines in a memory array are described. A first metal layer may be formed above a via that is configured to couple an access line of a memory array with a corresponding driver. The first metal layer may be oxidized, and then a second metal layer may be formed above the oxidized first metal layer. One or more access lines of the memory device may be formed from the second metal layer, the oxidized first metal layer, or both.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.