Methods and circuits for reducing clock jitter
US11831323B2 · kind B2 · utility
0Cited by
23References
18Claims
0Family size
Assignee
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Key dates
| Filing date | Apr 13, 2022 |
| Grant date | Nov 28, 2023 |
| Priority date | — |
| Expiry date | Apr 13, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/0334
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A clock-and-data recovery circuit for serial receiver includes a jitter meter and an adaptive loop gain adjustment circuitry. The clock-recovery circuitry phase aligns a clock signal to the incoming data. A jitter meter provides a measure of jitter, while adaptation circuitry uses the measure to adjust the clock-recovery circuitry in a manner that reduces clock jitter. The jitter measure can be a ratio of errors associated with different inter-symbol slew rates.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.