Method for preparing sample for wafer level failure analysis
US11835492B2 · kind B2 · utility
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3References
5Claims
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Key dates
| Filing date | Aug 20, 2021 |
| Grant date | Dec 5, 2023 |
| Priority date | — |
| Expiry date | Mar 1, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01N2203/0298
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
Embodiments of the present application provide a method for preparing a sample for wafer level failure analysis. The method includes that: a plurality of splitting points are formed on a surface of a selected region of a to-be-analyzed sample along a preset direction, the plurality of splitting points being arranged in a straight line; and the to-be-analyzed sample is split by taking the straight line where the plurality of splitting points are located as a splitting line, to expose a cross section of a side surface of the to-be-analyzed sample and form the sample for the wafer level failure analysis.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.