Implementing mapping data structures to minimize sequentially written data accesses
US11836076B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Feb 3, 2023 |
| Grant date | Dec 5, 2023 |
| Priority date | — |
| Expiry date | Feb 3, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/7201
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system includes a memory device, and a processing device, operatively coupled to the memory device, to perform operations including storing, on a volatile memory device, logical-to-physical (L2P) mapping data corresponding to sequentially written data, determining whether an L2P update criterion is satisfied, and in response to determining that the L2P update criterion is satisfied, updating an L2P mapping data structure based on the L2P mapping data. The L2P mapping data structure maintains an initial logical translation unit (LTU) of the sequentially written data, and a length of the sequentially written data from the initial LTU.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.