Memory-flow control register
US11836096B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 22, 2021 |
| Grant date | Dec 5, 2023 |
| Priority date | — |
| Expiry date | Jan 10, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4221
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Described apparatuses and methods relate to a memory-flow control register for a memory system that may support a nondeterministic protocol. To help manage the flow of memory requests in a system, a memory device can include logic, such as a hardware register, that can store values indicative of a total number of memory requests that are serviceable by the memory device at a time. The logic can be configured by device manufacturers during assembly. The manufacturers can determine the limits or capabilities of the system, based on the components and structures, and publish the capabilities, including QoS, based on the limits. When the memory device is connected to a host, the host can read the values and limit the number of memory requests sent to the device based on the values. Accordingly, the memory-flow control register can improve latency and bandwidth in accessing a memory device over an interconnect.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.