Memory with efficient DVS controlled by asynchronous inputs
US11837313B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 2, 2021 |
| Grant date | Dec 5, 2023 |
| Priority date | — |
| Expiry date | Jun 2, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/20
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory is provided that is configured to practice a sleep mode without retention in which a both bitcell array and a memory periphery are powered down responsive to an assertion of sleep mode without retention control signal. The sleep mode without retention control signal is also asserted during a DVS scan to power down the bitcell array. The memory includes a power management circuit that responds to an assertion of a DVS scan control signal to prevent the assertion of the sleep mode without retention control signal from causing a power down of the memory periphery during the DVS scan. The memory periphery may thus be thoroughly tested by the DVS scan because leakage current from the bitcell array is prevented by the powering down of the bitcell array.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.