Flip-chip package with reduced underfill area
US11837476B2 · kind B2 · utility
1Cited by
11References
9Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 15, 2020 |
| Grant date | Dec 5, 2023 |
| Priority date | — |
| Expiry date | May 18, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/181
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A flip-chip package and a method for assembling a flip-chip package includes positioning the die on a substrate and introducing an underfill material into a space between the die and the substrate, where a portion of the underfill material extends beyond an edge of the die and forms a fillet that at least partially surrounds the die. The underfill material is cured, and a portion of the fillet is removed to reduce the area of the fillet.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.