Coated semiconductor dies

US11837518B2 · kind B2 · utility

Assignee

• TEXAS INSTRUMENTS INCORPORATED · US

Inventors

• Michael Todd Wyant · Dallas, US
• Matthew John Sherbin · Dallas, US
• Christopher Daniel Manack · Flower Mound, US
• Patrick Francis Thompson · Allen, US
• You Chye How · Melaka City, MY

Key dates

• Filing date: Aug 26, 2020
• Grant date: Dec 5, 2023
• Expiry date: Sep 11, 2040

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L2924/3512
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

In examples, a chip scale package (CSP) comprises a semiconductor die; a conductive terminal coupled to the semiconductor die; and a non-conductive coat covering a backside of the semiconductor die and a sidewall of the semiconductor die. The non-conductive coat has a thickness of less than 45 microns.