Semiconductor package structure and method for manufacturing the same
US11837526B2 · kind B2 · utility
0Cited by
10References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 24, 2019 |
| Grant date | Dec 5, 2023 |
| Priority date | — |
| Expiry date | Jan 31, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D1/665
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor structure includes a molding compound having a first surface and a second surface opposite to the first surface, a passive device component disposed in the molding compound, a via penetrating the molding compound from the first surface to the second surface, a first connection structure disposed over the first surface of the molding compound and electrically coupled to the passive device component, and a second connection structure disposed over the second surface of the molding compound. The first connection structure and the second connection structure are electrically coupled to each other by the via.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.