Digital signal processors providing scalable decision feedback equalization (DFE) employing sequence selection and related methods
US11838153B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 29, 2022 |
| Grant date | Dec 5, 2023 |
| Priority date | — |
| Expiry date | Jun 29, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L25/03178
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A digital signal processor includes analog to digital converters to convert an analog voltage to digital voltage in unit intervals of an analog signal. A decision feedback equalizer (DFE) determines a first level of a digital sum of a digital voltage in a first UI and digital voltages of adjacent UIs (taps). The DFE identifies predetermined sequences of levels of consecutive UIs that include the first level and selects one of the predetermined sequences to decode digital data encoded in the analog signal in the UI. The DSP may be programmable to include taps from UIs that may affect the first UI. The predetermined sequences may include levels of the digital sums of consecutive UIs of the analog signal. The predetermined sequences may be identified in a look-up table based on the first level.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.