Three-dimensional vertical single transistor ferroelectric memory and manufacturing method thereof

US11839085B2 · kind B2 · utility

Assignee

• INSTITUTE OF MICROELECTRONICS OF THE CHINESE ACADEMY OF SCIENCES · CN

Inventors

• Huaxiang Yin · Beijing, CN
• Zhaozhao Hou · Beijing, CN
• Tianchun Ye · Beijing, CN
• Chaolei Li · Beijing, CN

Key dates

• Filing date: Nov 4, 2019
• Grant date: Dec 5, 2023
• Expiry date: Sep 1, 2040

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D64/689

Abstract

Provided are a three-dimensional vertical single transistor ferroelectric memory and a manufacturing method thereof. The ferroelectric memory comprises: a substrate; an insulating dielectric layer provided at the substrate; a channel structure extending through the insulating dielectric layer and connected to the substrate, the channel structure having a source/drain region and a channel region connected to the source/drain region; and a gate stack structure arranged around the channel structure and provided in the insulating dielectric layer opposite to the channel region, the gate stack structure comprising a ferroelectric insulation layer and a gate sequentially stacked in a direction away from the channel structure. The ferroelectric memory having the above structure can replace conventional DRAMs. Therefore, the invention realizes a high intensity high speed memory.