Semiconductor memory devices with ECC engine defect determination based on test syndrome, test parity, expected decoding status and received decoding status
US11841763B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 26, 2021 |
| Grant date | Dec 12, 2023 |
| Priority date | — |
| Expiry date | Nov 27, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/1206
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory device includes a buffer die and a plurality of memory dies. Each of the memory dies includes a memory cell array, an error correction code (ECC) engine and a test circuit. The memory cell array includes a plurality of memory cell rows, each including a plurality of volatile memory cells. The test circuit, in a test mode, generates a test syndrome and an expected decoding status flag indicating error status of the test syndrome, receives test parity data generated by the ECC engine based on the test syndrome and a decoding status flag indicating error status of the test parity data, and determines whether the ECC engine has a defect based on comparison of the test syndrome and the test parity data and a comparison of the expected decoding status flag and the decoding status flag.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.