Single chip multi-die architecture having safety-compliant cross-monitoring capability
US11841776B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 12, 2019 |
| Grant date | Dec 12, 2023 |
| Priority date | — |
| Expiry date | Nov 22, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/1654
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods, systems and apparatuses may provide for technology that includes a chip having a first die including a first processing logic to execute a first application instance and generate a first output of the first application instance, and a second processing logic to execute a second application instance and generate a second output of the second application instance. The chip may also include a second die coupled to the first die, wherein the second die includes a safety monitor detect a condition associated with one or more of an error in the first output, an error in the second output, or a discrepancy between the first output and the second output. The safety monitor may also initiate a transition of the chip into a safe state in response to the condition.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.