Patent · US Active

Tamper detection and response techniques

US11841943B2 · kind B2 · utility

0Cited by

0References

20Claims

0Family size

Assignee

Arm Limited · GB

Inventors

Joshua Randall · Austin, US
Joel Thornton Irby · Austin, US
Carl Wayne Vineyard · Cedar Park, US
Mudit Bhargava · Austin, US

Key dates

Filing date	Sep 26, 2019
Grant date	Dec 12, 2023
Priority date	—
Expiry date	Oct 12, 2042

Classification

Technology area (CPC G)Physics
CPC primaryG11C16/22
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

Various implementations described herein refer to a method for tracking abnormal incidents while monitoring activity of logic circuitry. The method may include detecting a tamper event related to the abnormal incidents and storing an attack signature related to the tamper event. The attack signature may be stored in non-volatile memory (NVM), such as, e.g., correlated electron random access memory (CeRAM).

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.