Semiconductor structure and manufacturing method thereof
US11842920B2 · kind B2 · utility
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1References
20Claims
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Key dates
| Filing date | Jun 21, 2021 |
| Grant date | Dec 12, 2023 |
| Priority date | — |
| Expiry date | Sep 21, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/519
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present disclosure provides a semiconductor structure, including a transistor. The transistor includes a semiconductive substrate, a gate structure, a pair of highly doped regions and a dielectric element. The semiconductive substrate has a top surface. The gate structure is over the top surface. The pair of highly doped regions is separated by the gate structure. The dielectric element is embedded in the semiconductive substrate. The dielectric element is laterally and vertically misaligned with the pair of highly doped regions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.