Selective low temperature epitaxial deposition process
US11843033B2 · kind B2 · utility
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20Claims
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Key dates
| Filing date | Apr 15, 2021 |
| Grant date | Dec 12, 2023 |
| Priority date | — |
| Expiry date | Jun 2, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/121
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for the selective formation of epitaxial layers is described herein. In the method, epitaxial layers are deposited to form source and drain regions around a horizontal gate all around (hGAA structure). The method includes co-flowing a combination of chlorinated silicon containing precursors, antimony containing precursors, and n-type dopant precursors. The resulting source and drain regions are selectively grown from crystalline nanosheets or nanowires of the hGAA structure over the non-crystalline gate structure and dielectric layers. The source and drain regions are predominantly grown in a <110> direction.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.