Integration of p-channel and n-channel E-FET III-V devices without parasitic channels
US11843047B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 24, 2022 |
| Grant date | Dec 12, 2023 |
| Priority date | — |
| Expiry date | May 24, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/602
Abstract
In some embodiments, the present disclosure relates to an integrated transistor device, including a first barrier layer arranged over a substrate. Further, an undoped layer may be arranged over the first barrier layer and have a n-channel device region laterally next to a p-channel device region. The n-channel device region of the undoped layer has a topmost surface that is above a topmost surface of the p-channel device region of the undoped layer. The integrated transistor device may further comprise a second barrier layer over the n-channel device region of the undoped layer. A first gate electrode is arranged over the second barrier layer, and a second gate electrode is arranged over the p-channel device region of the undoped layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.