Buffer and methods for address translations in a processor
US11847064B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Dec 7, 2018 |
| Grant date | Dec 19, 2023 |
| Priority date | — |
| Expiry date | Mar 22, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/683
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and system of translating addresses is disclosed that includes receiving an effective address for translation, providing a processor and a translation buffer where the translation buffer has a plurality of entries, wherein each entry contains a mapping of an effective address directly to a corresponding real address, and information on a corresponding intermediate virtual address. The method and system further include determining whether the translation buffer has an entry matching the effective address, and in response to the translation buffer having an entry with a matching effective address, providing the real address translation from the entry having the matching effective address.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.