Systems, methods, and apparatus for tile configuration
US11847452B2 · kind B2 · utility
5Cited by
95References
20Claims
0Family size
Assignee
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Key dates
| Filing date | Jun 28, 2021 |
| Grant date | Dec 19, 2023 |
| Priority date | — |
| Expiry date | Jun 28, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/455
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Embodiments detailed herein relate to matrix (tile) operations. For example, decode circuitry to decode an instruction having fields for an opcode and a memory address; and execution circuitry to execute the decoded instruction to set a tile configuration for the processor to utilize tiles in matrix operations based on a description retrieved from the memory address, wherein a tile a set of 2-dimensional registers are discussed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.