System for error detection and correction in a multi-thread processor
US11847457B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | May 31, 2022 |
| Grant date | Dec 19, 2023 |
| Priority date | — |
| Expiry date | May 31, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3877
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A master processor is configured to execute a first thread and a second thread designated to run a program in sequence. A slave processor is configured to execute a third thread to run the program in sequence. An instruction fetch compare engine is provided. The first thread initiates a first thread instruction fetch for the program and stored in an instruction fetch storage. Retrieved data associated with the fetched first thread instruction is stored in a retrieved data storage. The second thread initiates a second thread instruction fetch for the program. The instruction fetch compare logic compares the second thread instruction fetch for the program with the first thread instruction fetch stored in the instruction fetch storage for a match. When there is a match, the retrieved data associated with the fetched first thread instruction is presented from the retrieved data storage, in response to the second thread instruction fetch.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.