Memory devices with dynamic program verify levels
US11848060B2 · kind B2 · utility
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2References
20Claims
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Key dates
| Filing date | Feb 8, 2023 |
| Grant date | Dec 19, 2023 |
| Priority date | — |
| Expiry date | Feb 8, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/5671
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Memory devices might include an array of memory cells and a controller configured to access the array of memory cells. The controller may sense a first threshold voltage of the selected memory cell. In response to the sensed first threshold voltage being between a first pre-program verify level and a first program verify level, the controller may bias the selected memory cell to a first voltage level. The first pre-program verify level might be less than a final pre-program verify level and the first program verify level might be less than a final program verify level.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.