Voltage control method and voltage control circuit for anti-fuse memory array
US11848062B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 1, 2020 |
| Grant date | Dec 19, 2023 |
| Priority date | — |
| Expiry date | Sep 1, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C17/16
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A voltage control method and a voltage control circuit for an anti-fuse memory array, including: obtaining a storage data address, dividing the storage data address into multiple subdata addresses, decoding each subdata address to obtain a corresponding group of decoder output signals, converting the corresponding group of decoder output signals into a group of control signals by a corresponding group of high voltage converters; connecting multiple groups of data selectors in series, outputting selection voltages input to each group of data selectors to an anti-fuse unit under the control of the corresponding group of control signals; programming or reading an anti-fuse unit; the selection voltages include one of a programming selection voltage, a reading selection voltage, and a non-designated selection voltage. The present disclosure reduces the number of transistors and saves layout areas when the programming or reading operation is performed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.