Patent · US Active

Low-latency retimer with seamless clock switchover

US11853115B1 · kind B1 · utility

0Cited by

4References

18Claims

0Family size

Assignee

Astera Labs, Inc. · US

Inventors

Jitendra Mohan · Palo Alto, US
Subbarao Arumilli · Cupertino, US
Charan Enugala · Newark, US
Chi Feng · San Jose, US
Ken (Keqin) Han · Fremont, US
Pulkit Khandelwal · Cupertino, US
Vikas Khandelwal · San Jose, US
Casey Morrison · San Jose, US
Enrique Musoll · San Jose, US
Vivek Trivedi · Fremont, US

Key dates

Filing date	Sep 27, 2022
Grant date	Dec 26, 2023
Priority date	—
Expiry date	Sep 27, 2042

Classification

Technology area (CPC H)Electricity
CPC primaryH03K2005/00019
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

A low-latency signaling link retimer generates an output signal transmission synchronously with respect to a core clock signal alternately selected from two or more plesiochronous or mesochronous clock sources with switchover between or among the core-clock sources executed without shrinking, extending or otherwise disrupting the edge-to-edge core clock period or clock duty cycle.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.