Independent operation of an ethernet switch integrated on a system on a chip
US11853772B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 16, 2022 |
| Grant date | Dec 26, 2023 |
| Priority date | — |
| Expiry date | Aug 16, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L49/351
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
An Ethernet switch and a switch microcontroller or CPU are integrated onto a system-on-a-chip (SoC). The Ethernet switch remains independently operating at full speed even though the remainder of the SoC is being reset or is otherwise nonoperational. The Ethernet switch is on a separated power and clock domain from the remainder of the integrated SoC. A warm reset signal is trapped by control microcontroller (MCU) to allow the switch CPU to isolate the Ethernet switch and save state. When the Ethernet switch is isolated and operating independently, the warm reset request is provided to the other entities on the integrated SoC. When warm reset is completed, the state is restored and the various DMA and flow settings redeveloped in the integrated SoC to allow return to normal operating condition.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.