Semiconductor memory structure and fabrication method thereof
US11854632B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 15, 2021 |
| Grant date | Dec 26, 2023 |
| Priority date | — |
| Expiry date | Jul 21, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2216/26
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory structure includes a substrate having thereon a transistor forming region and a capacitor forming region. A transistor is disposed on the substrate within the transistor forming region. A capacitor is disposed within the capacitor forming region and electrically coupled to the transistor. A first inter-layer dielectric layer covers the transistor forming region and the capacitor forming region. The first inter-layer dielectric layer surrounds a metal gate of the transistor and a bottom plate of the capacitor. A cap layer is disposed on the first inter-layer dielectric layer. The cap layer has a first thickness within the transistor forming region and a second thickness within the capacitor forming region. The first thickness is greater than the second thickness. The cap layer within the capacitor forming region acts as a capacitor dielectric layer of the capacitor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.