Systems and methods for improved dual-tail latch with wide input common mode range
US11854651B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Feb 22, 2022 |
| Grant date | Dec 26, 2023 |
| Priority date | — |
| Expiry date | Aug 6, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K3/356139
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device including an interface to receive one or more clock signals and one or more data signal a dual-sensing stage dual-tail latch arranged at the interface. The dual-sensing stage dual-tail latch includes a sensing stage to sense a differential voltage between a first signal and a second signal and to provide a first differential voltage output and a second differential voltage output to a first node and a second node, respectively. The dual-sensing stage dual-tail latch includes a complimentary sensing stage arranged in parallel with the sensing stage and to sense the differential voltage between the first signal and the second signal, where a first complimentary differential output voltage and a second complimentary differential output of the complimentary sensing stage are coupled to the first node and the second node. The dual-sensing stage dual-tail latch includes a latch stage to receive the outputs from the first node and the second node.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.