Patent · US Active

Gate spacer patterning

US11854803B2 · kind B2 · utility

0Cited by

8References

18Claims

0Family size

Assignee

IMEC VZW · BE

Inventors

Boon Teik Chan · Wilsele, BE
Pierre Morin · Albany, US
Antony Premkumar Peter · Heverlee, BE

Key dates

Filing date	Jul 9, 2021
Grant date	Dec 26, 2023
Priority date	—
Expiry date	Dec 22, 2041

Classification

Technology area (CPC H)Electricity
CPC primaryH10D30/62
WIPO fieldSemiconductors
WIPO sectorElectrical engineering

Abstract

A method for protecting a gate spacer when forming a FinFET structure, the method comprising: providing a fin with at least one dummy gate crossing the fin wherein a gate hardmask is present on top of the dummy gate; providing a gate spacer such that it is covering the dummy gate and the gate hardmask; recessing the gate spacer such that at least a part of the gate hardmask is exposed; selectively growing, by means of area selective deposition, extra capping material over the exposed part of the gate hardmask.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.