Pierre Morin
78Patents
7h-index
62Co-inventors
75Inventor score
Filing activity: Apr 23, 2001 → Feb 28, 2024
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US8952420B1 | Method to induce strain in 3-D microfabricated structures | Electricity | 17 | Active |
| US9000498B2 | FinFET with multiple concentration percentages | Electricity | 11 | Active |
| US9236474B2 | Method to form strained channel in thin box SOI structures by elastic strain relaxation of the substrate | Electricity | 10 | Active |
| US9607901B2 | Integrated tensile strained silicon NFET and compressive strained silicon-germanium PFET implemented in FINFET technology | Electricity | 9 | Active |
| US7187038B2 | Semiconductor device with MOS transistors with an etch-stop layer having an improved residual stress level and method for fabricating such a semiconductor device | Electricity | 8 | Expired |
| US9466718B2 | Semiconductor device with fin and related methods | Electricity | 7 | Active |
| USD631109S1 | Foot pad for tilting inversion exerciser | General | 7 | Expired |
| US9252208B1 | Uniaxially-strained FD-SOI finFET | Electricity | 7 | Active |
| US9245953B2 | Method to induce strain in 3-D microfabricated structures | Electricity | 6 | Active |
| US9548361B1 | Method of using a sacrificial gate structure to make a metal gate FinFET transistor | Electricity | 6 | Active |
| US9099559B2 | Method to induce strain in finFET channels from an adjacent region | Electricity | 5 | Active |
| US9406783B2 | Method to induce strain in finFET channels from an adjacent region | Electricity | 5 | Active |
| US9431538B2 | Enhanced method of introducing a stress in a transistor channel by means of sacrificial sources/drain regions and gate replacement | Electricity | 5 | Active |
| US10483393B2 | Method to induce strain in 3-D microfabricated structures | Electricity | 4 | Active |
| US9647086B2 | Early PTS with buffer for channel doping control | Electricity | 4 | Active |
| US10515965B2 | Method to induce strain in finFET channels from an adjacent region | Electricity | 4 | Active |
| US9679899B2 | Co-integration of tensile silicon and compressive silicon germanium | Electricity | 4 | Active |
| US6582258B2 | Floating track device | Performing Operations; Transporting | 4 | Expired |
| US10043805B2 | Method to induce strain in finFET channels from an adjacent region | Electricity | 4 | Active |
| US9166049B2 | Method to enhance strain in fully isolated finFET structures | Electricity | 4 | Active |
| US9806196B2 | Semiconductor device with fin and related methods | Electricity | 3 | Active |
| US10177255B2 | Semiconductor device with fin and related methods | Electricity | 3 | Active |
| US9287130B1 | Method for single fin cuts using selective ion implants | Electricity | 3 | Active |
| US10847654B2 | Method to induce strain in 3-D microfabricated structures | Electricity | 2 | Active |
| US10418488B2 | Method to form strained channel in thin box SOI structures by elastic strain relaxation of the substrate | Electricity | 2 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.