Cu3Sn via metallization in electrical devices for low-temperature 3D-integration
US11854879B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 25, 2021 |
| Grant date | Dec 26, 2023 |
| Priority date | — |
| Expiry date | Sep 30, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3656
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A Cu3Sn electrical interconnect and method of making same in an electrical device, such as for hybrid bond 3D-integration of the electrical device with one or more other electrical devices. The method of forming the Cu3Sn electrical interconnect includes: depositing a Sn layer in the via hole; depositing a Cu layer atop and in contact with the Sn layer; and heating the Sn layer and the Cu layer such that the Sn and Cu layers diffuse together to form a Cu3Sn interconnect in the via hole. During the heating, a diffusion front between the Sn and Cu layers moves in a direction toward the Cu layer as initially deposited, such that any remaining Cu layer or any voids formed during the diffusion are at an upper region of the formed Cu3Sn interconnect in the via hole, thereby allowing such voids or remaining material to be easily removed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.