Three-dimensional integrated system of dram chip and preparation method thereof
US11854939B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Jul 2, 2020 |
| Grant date | Dec 26, 2023 |
| Priority date | — |
| Expiry date | Jul 10, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B80/00
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Disclosed is a three-dimensional integrated system for DRAM chips and a fabrication method thereof. A plurality of trench structures are etched on the front and back of a silicon wafer; then, a TSV structure is etched between the two upper and lower trenches opposite to each other for electrical connection; then, DRAM chips are placed in the trenches, and copper-copper bonding is used to make the chips electrically connected to the TSV structure in a vertical direction; finally, redistribution is done to make the chips in a horizontal direction electrically connected. The invention can make full use of silicon materials, and can avoid problems such as warpage and deformation of an interposer. In addition, placing the chips in the trenches will not increase the overall package thickness, while protecting the chips from external impact.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.