Qingqing Sun
25Patents
2h-index
22Co-inventors
53Inventor score
Filing activity: Dec 24, 2010 → Nov 8, 2024
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US9153500B2 | Method for improving the electromigration resistance in the copper interconnection process | Electricity | 4 | Active |
| US8748267B2 | Method for manufacturing a tunneling field effect transistor with a U-shaped channel | Electricity | 3 | Active |
| US8486754B1 | Method for manufacturing a gate-control diode semiconductor device | Electricity | 2 | Active |
| US9508811B2 | Semi-floating-gate device and its manufacturing method | Electricity | 2 | Active |
| US10726028B2 | Method and apparatus for matching names | Physics | 2 | Active |
| US9054303B2 | Metal-oxide-semiconductor (MOS) transistor structure integrated with a resistance random access memory (RRAM) and the manufacturing methods thereof | Electricity | 2 | Active |
| US9431506B2 | Metal-oxide-semiconductor (MOS) transistor structure integrated with a resistance random access memory (RRAM) and the manufacturing methods thereof | Electricity | 1 | Active |
| US8860179B2 | Inductive loop formed by through silicon via interconnection | Electricity | 1 | Active |
| US8574958B2 | Method for manufacturing a gate-control diode semiconductor memory device | Electricity | 1 | Active |
| US8586432B2 | Method for manufacturing vertical-channel tunneling transistor | Electricity | 1 | Active |
| US9147835B2 | Tunnel transistor structure integrated with a resistance random access memory (RRAM) and a manufacturing method thereof | Electricity | 1 | Active |
| US10699076B2 | Risk address identification method and apparatus, and electronic device | Physics | 1 | Active |
| US10762296B2 | Risk address identification method and apparatus, and electronic device | Physics | 1 | Active |
| US9263351B2 | Method of forming an integrated inductor by dry etching and metal filling | Electricity | 0 | Active |
| US9099178B2 | Resistive random access memory with electric-field strengthened layer and manufacturing method thereof | Physics | 0 | Active |
| US8994095B2 | Semiconductor memory device with a buried drain and its memory array | Electricity | 0 | Active |
| US11854939B2 | Three-dimensional integrated system of dram chip and preparation method thereof | Electricity | 0 | Active |
| US11881442B2 | SOI active transfer board for three-dimensional packaging and preparation method thereof | Electricity | 0 | Active |
| US8426271B1 | Method for manufacturing a gate-control diode semiconductor memory device | Electricity | 0 | Active |
| US9748406B2 | Semi-floating-gate device and its manufacturing method | Electricity | 0 | Active |
| US11887912B2 | Through silicon via structure for three-dimensional integrated circuit packaging and manufacturing method thereof | Electricity | 0 | Active |
| US8455372B2 | Method for cleaning and passivating gallium arsenide surface autologous oxide and depositing AL203 dielectric | Electricity | 0 | Active |
| US12360075B1 | Construction method and application of microRNA electrochemical biosensor | Chemistry; Metallurgy | 0 | Active |
| US12159179B2 | Three-dimensional integrated system of RFID chip and super capacitor and preparation method thereof | Emerging Cross-Sectional Technologies | 0 | Active |
| US11869827B2 | Three-dimensional capacitor-inductor based on high functional density through silicon via structure and preparation method thereof | Electricity | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.