Boundary design for high-voltage integration on HKMG technology
US11855091B2 · kind B2 · utility
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20Claims
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Key dates
| Filing date | Jul 19, 2022 |
| Grant date | Dec 26, 2023 |
| Priority date | — |
| Expiry date | Jul 19, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/0142
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present disclosure relates to an integrated circuit (IC) that includes a boundary region defined between a low voltage region and a high voltage region, and a method of formation. In some embodiments, the integrated circuit comprises an isolation structure disposed in the boundary region of the substrate. A first polysilicon component is disposed over the substrate alongside the isolation structure. A boundary dielectric layer is disposed on the isolation structure. A second polysilicon component is disposed on the sacrifice dielectric layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.