SOI device structure for robust isolation
US11855137B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 4, 2022 |
| Grant date | Dec 26, 2023 |
| Priority date | — |
| Expiry date | Feb 4, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/393
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
This disclosure provides for robust isolation across the SOI structure. In contrast to forming a charge trap layer in specific areas on the structure, a charge trap layer may be built across the insulating/substrate interface. The charge trap layer may be an implantation layer formed throughout and below the insulation layer. Devices built on this SOI structure have reduced cross-talk between the devices. Due to the uniform structure, isolation is robust across the structure and not confined to certain areas. Additionally, deep trench implantation is not required to form the structure, eliminating cost. The semiconductor-on-insulator substrate may include an active silicon layer over an oxide layer. The oxide layer may be over a charge trap layer. The charge trap layer may be over a silicon substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.