Efficient hard decision decoding of generalized Reed-Solomon codes in presence of erasures and errors within the singleton bound
US11855658B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 5, 2022 |
| Grant date | Dec 26, 2023 |
| Priority date | — |
| Expiry date | Aug 5, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/3761
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A processing circuit is configured to: construct a first locator polynomial for a Reed-Solomon codeword to identify locations of erasures in the Reed-Solomon codeword; determine a first syndrome of the Reed-Solomon codeword; calculate a first error evaluator polynomial from the first syndrome and the first locator polynomial; and perform error detection based on the first error evaluator polynomial to determine presence of errors in the Reed-Solomon codeword. When presence of errors in the Reed-Solomon codeword is not detected in the error detection, the processing circuit bypasses updating the first locator polynomial and proceeds to completing decoding of the Reed-Solomon codeword, but when presence of errors in the Reed-Solomon codeword is detected in the error detection, the system first updates the first locator polynomial to a second locator polynomial in a process with reduced complexity compared to the common one, before completing decoding of the Reed-Solomon codeword.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.