Method for manufacturing memory and same

US11856758B2 · kind B2 · utility

Assignee

• CHANGXIN MEMORY TECHNOLOGIES, INC. · CN

Inventors

• Er-Xuan Ping · Boise, US
• Zhen Zhou · Emeryville, US
• Lingguo Zhang · Hefei, CN

Key dates

• Filing date: Sep 28, 2021
• Grant date: Dec 26, 2023
• Expiry date: Mar 25, 2042

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10B12/482

Abstract

A method for manufacturing a memory includes: providing a substrate and multiple discrete pseudo bit line contact layers, a plurality of active areas being provided in the substrate, and each bit line contact layer being electrically connected to the active areas; forming pseudo bit line structures at tops of the pseudo bit line contact layers; forming sacrificial layers that fill regions between the adjacent pseudo bit line structures and are located on side walls of the pseudo bit line structures and the pseudo bit line contact layers; after forming the sacrificial layers, removing the pseudo bit line structures to form through holes exposing the pseudo bit line contact layers; removing the pseudo bit line contact layers to form through holes in the substrate; and forming bit line contact layers that fill the through holes in the substrate and are electrically connected to the active areas.