Structure of 3D NAND memory device and method of forming the same
US11856776B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 28, 2021 |
| Grant date | Dec 26, 2023 |
| Priority date | — |
| Expiry date | Apr 1, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/037
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of forming a structure of 3D NAND memory device, including steps of forming a first stack layer on a substrate, forming a first channel hole extending through the first stack layer, forming a block layer on a surface of the first stack layer and the first channel hole, forming a sacrificial layer in the first channel hole, forming a second stack layer on the first stack layer and the sacrificial layer, performing a first etch process to form a second channel hole extending through the second stack layer and at least partially overlapping the first channel hole and to remove the sacrificial layer in the first channel hole, removing the block layer exposed from the second channel hole, and forming a function layer on a surface of the first channel hole and the second channel hole.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.