Wafer breaking method and chip failure analysis method
US11860073B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Apr 25, 2022 |
| Grant date | Jan 2, 2024 |
| Priority date | — |
| Expiry date | Jul 28, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L22/12
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
Embodiments of the present disclosure relate to a wafer breaking method and a chip failure analysis method. The wafer breaking method includes: providing a wafer sample, which includes a first surface with a target point and a second surface opposite to the first surface; forming a first crack and a second crack, orthographic projection of which on the first surface are on the same straight line as the target point in a preset direction; forming a cutting slot, there is a preset distance between a bottom of the cutting slot and the first surface, and orthographic projection of the first crack and the second crack are on the same straight line as the cutting slot; and breaking the wafer sample along the cutting slot, such that the wafer sample is broken in the preset direction to obtain a cross section of the target point in the preset direction.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.