Peripheral device protocols in confidential compute architectures
US11860797B2 · kind B2 · utility
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Key dates
| Filing date | Dec 30, 2021 |
| Grant date | Jan 2, 2024 |
| Priority date | — |
| Expiry date | Dec 30, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/603
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Restricting peripheral device protocols in confidential compute architectures, the method including: receiving a first address translation request from a peripheral device supporting a first protocol, wherein the first protocol supports cache coherency between the peripheral device and a processor cache; determining that a confidential compute architecture is enabled; and providing, in response to the first address translation request, a response including an indication to the peripheral device to not use the first protocol.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.